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  • Dr. Meenakshi Agarwal Assistant Professor
    • School Schools of Engineering and Technology
    • Department/Programme B.Tech EC
    • Email Meenakshi.agarwal1@bmu.edu.in

    Dr. Meenakshi Agarwal comes from a family of educationists in Electronics and Communication. Have completed her PhD in VLSI Design with a fellowship from University of Delhi. She is working as an Assistant Professor in BMU campus.

    • Digital Electronics
    • Digital Hardware Design
    • Analog Electronics
    • Signal and System
    • Graduation In: (B.Tech.) Electronics and Communication
    • Graduation From: U.P. Technical University
    • Graduation Year: 2005
    • Post Graduation In: M.Tech. VLSI Design
    • Post Graduation From: NIT, Kurukshetra, Deemed University
    • Post Graduation Year: 2009
    • Doctorate In: PhD – VLSI Design
    • Doctorate From: University of Delhi
    • Doctorate Year: 2018
    From - To (Year)Designation & Organization
    2018-currentAssistant Professor - BMU
    2012-2016Teaching and research fellow – Netaji Subhas Institute of Technology (NSIT), Delhi
    2011-2012Assistant Professor – NIEC, Delhi
    2009-2011Assistant Professor- AKGEC, Ghaziabad
    2006-2007Lecturer, VIET, Dadri
    • Digital Filters
    • Digital Circuits
    • Digital Signal Processing
    • Solar energy
    • Meenakshi Agarwal and Tarun Kumar Rawat , “VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate”, *Radioengineering Journal, U.S.A., 2016.
    • Richa Barsainya, Meenakshi Agarwal and Tarun Kumar Rawat, “Design and FPGA Implementation of Multiplierless Comb Filter”, International Journal of Circuit theory and applications, Wiely, Vol 45, Issue 11, Pages 1497-1513, 2017.
    • Meenakshi Agarwal, Tarun Kumar Rawat “VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency”, Computer engineering and information technology, SciTechnol, vol. 4, issue 4, 2015, http://dx.doi.org/10.4172/2324-9307.1000138.
    • Best Paper Award in 2009 technical paper presentation at NIT, Kurukshetra
    • Supervised numerous M.Tech. Thesis and B.Tech. projects.
    • GATE (Graduate Aptitude Test in Engineering), 2007
    • Avi Gosvami, Meenakshi Agarwal, Tarun kumar Rawat, kunvar Singh, FPGA Implementation of Reconfigurable Architecture for Half-band FIR Filters, 4th International conference on ‘Signal Processing, Computing and Control (ISPCC-2017)’, 2017.
    • Meenakshi Agarwal, Richa Barsainya, Tarun Kumar Rawat, “FPGA Implementation of Hilbert Transformer Based on Lattice Wave Digital Filter”, Reliability, Infocom Technologies and Optimization (ICRITO)(Trends and Future Directions), 2015 4th International Conference on. IEEE, 2015.
    • Meenakshi Agarwal, Richa Barsainya and Tarun Kumar Rawat , “Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA”, Signal Processing and Integrated Networks (SPIN), Feb 2016, 3rd international conference on IEEE.
    • Meenakshi Agarwal, Richa Barsainya and Tarun Kumar Rawat , “Low Power Reconfigurable Parametric Equalizer Design with Row Bypassing Multiplier on FPGA”, IEEE international conference on Computing Communication and Automation ( ICCCA), 2016.
    • Meenakshi Agarwal, Radha Agarwal, “Design of Low Power Low Voltage 1-bit Full Adder”, proceeding of IEEE ICIT09, 2009 .
    • Meenakshi Agarwal, Radha Agarwal, “Techniques for Power Reduction in CMOS Design”, proceeding of IEEE, BEATS- 2010.
    • Richa Barsainya, Meenakshi Agarwal, Tarun Kumar Rawat, “ Multiplier-less Implementation of Quadrature Mirror Filter”, Reliability, Infocom Technologies and Optimization (ICRITO)(Trends and Future Directions), 2015 4th International Conference on. IEEE, 2015.
    • Richa Barsainya, Meenakshi Agarwal, Tarun Kumar Rawat, “Minimum Multiplier Implementation of a Comb Filter using Lattice Wave Digital Filter”, proceeding of IEEE India international conference INDICON, DEC. 2015.
    • Richa Barsainya, Meenakshi Agarwal and Tarun Kumar Rawat , “Design and Implementation of Fractional Order Integrator with Reduced Hardware”, Signal Processing and Integrated Networks (SPIN), Feb 2016, 3rd international conference on IEEE.

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